1. Technical Field
The present invention relates to a wiring board and a method of manufacturing the same. More particularly, the present invention relates to a wiring board for mounting semiconductor chips, semiconductor components, and other mounting components thereon, or a wiring board for mounting semiconductor chips, semiconductor components, and other mounting components thereon, and establishing connection with another board (e.g., a package for flip-chip connection), and a method of manufacturing the same.
2. Background Art
When semiconductor chips, semiconductor components, and other mounting components are mounted on a wiring board, generally, the part, except for the portions (which are generally referred to as “pads”) necessary for connection with chips and the like in mounting of wiring on the outermost layer of the wiring board, is protected using a resin material referred to as a solder resist for protection from adhesion of solder, contamination, and the like. In that case, exposure of the wiring portions necessary for connection is accomplished by a photolithography method, a screen printing method, a laser processing method, or the like. According to a photolithography method, by use of a photosensitive one as a resin material for the solder resist, patterning by exposure to light and development is carried out. According to a screen printing method, by use of a printing mask, a resin material is printed on only necessary portions. According to laser processing, a resin material is coated on the entire surface, and then, the resin material on the region to be exposed is removed by laser light irradiation.
As one example, a description will be given to exposure of pads by patterning with photolithography of an insulation resin (solder resist) in the related art. As shown in FIG. 12A, on an insulation board 101, a required number of underlying wirings 102 and an insulation layer 103 covering them are formed. Then, an uppermost wiring layer 104 and an insulation resin (solder resist) layer 105 covering it are formed. Subsequently, the insulation resin layer 105 is exposed and developed through photolithography, thereby forming openings in a prescribed pattern as shown in FIG. 12B. As a result, portions of the uppermost wiring 104 are exposed as pads 106 (top side) and 106′ (bottom side).
In the case by a screen printing method, after forming the elements including up to the uppermost wiring layer 104 of FIG. 12A, an insulation resin is screen printed by the use of a mask having a prescribed pattern, thereby forming an insulation resin layer having the same opening pattern as that shown in FIG. 12B.
It is also known that pads are exposed at the wiring board surface using a sandblast method. In this case, a resist mask for sandblast including openings formed at the portions corresponding to the pads to be exposed is formed. Thus, an air flow containing abrasive grains is applied to the openings to expose the pad portions. For example, in Japanese Unexamined Patent Documents: JP-A-2000-286362, JP-A-2000-294678 and JP-A-2001-7240, a sandblast method for exposure of pads is described.
A conventional example of exposure of pads by a sandblast method will be described by reference to views showing one pad formation region on an enlarged scale. As shown in FIG. 13A, on an insulation board 201 (of which only one side is shown), a required number of underlying wirings 202 and an insulation layer 203 covering them are formed. Then, an uppermost wiring layer 204 and an insulation resin layer 205 covering it are formed thereon. As shown in FIG. 13B, a dry film resist (DFR) 206 for sandblast is laminated on the insulation resin layer 205, and openings in a prescribed pattern are formed through exposure/development. Then, as shown in FIG. 13C, abrasive grains 207 are sprayed to the openings so that the insulation resin is removed. As a result, a part of the wiring layer 204 is exposed and used as a pad 208. Thereafter, as shown in FIG. 13D, the DFR for sandblast is removed.
On the other hand, in the field of wafer level chip scale package (WL-CSP), the following is described. Namely, cylindrical pads formed on a conductive layer of the semiconductor chip are covered with a resin, and the pad surfaces are exposed by polishing or etching (see Japanese Unexamined Patent Document: JP-A-2004-48048).
In accordance with a recent trend for smaller size and higher precision of semiconductor chips, a wiring board for mounting them has also been decreasing in size and increasing in precision of the connection terminal. However, the solder resist (protective resin) of the outermost layer of the wiring board is required to have electric characteristics such as insulation reliability, and chemical characteristics such as adhesion with an underfill, a mold resin, or the like, necessary for mounting. Further, for the reliability improvement, there are also requirements as to the clearance between the pad in the resin layer opening and the opening inner wall, or the opening shape. It is not easy to design the composition of the solder resist so as to meet all the requirements. Particularly, in the case of the formation of openings with photolithography requiring the use of a photosensitive solder resist material, it is difficult to improve the dimensional precision of the opening. Further, in the case of photolithography, there is also a problem of misalignment of a photomask, which also causes impediment to the improvement of the dimensional precision of the opening.
According to a technique of screen printing or laser processing, the solder resist layer is not directly patterned by photolithography (a solder resist to which photosensitivity has been imparted is not used). Therefore, the technique is advantageous in terms of the chemical composition of the solder resist. However, in the case of screen printing, there is also a problem of misalignment of the printing mask. Further, it is not easy to form a fine pattern necessary for the reduction in size and the enhancement in precision with a printing method. The problem of misalignment also applies to the case of laser processing. Whereas, in the case of laser processing, variations in processing dimensions or shape are unavoidable.
According to the sandblast method, the solder resist layer is not directly patterned by photolithography. Therefore, the technique is also advantageous in terms of the chemical composition of the solder resist. However, also in this case, when the position of the resist mask for sandblast is shifted, the pads of necessary position/area become impossible to expose. Therefore, high precision alignment of the mask becomes necessary. However, the wiring board largely changes in dimensions with temperature changes and processing. In the case of fine wiring, high precision alignment between the portion to be exposed and the resist mask for sandblast becomes difficult. For this reason, for exposure of pads with a sandblast method in the related art, the width of the uppermost layer wiring 204 must be formed wider (e.g., by about 10 μm per side) than the width necessary for the pad in view of the misalignment between the opening to be formed by sandblast and the uppermost layer wiring 204 including the pad portion to be exposed shown in FIG. 13D. The excess amount of the wiring width becomes disadvantageous in terms of design when the wiring pitch is narrowed with a reduction in size of mounting components.
Thus, it has become increasingly difficult to expose a pad for connection with a surface-mounted component from a resin layer such as a solder resist of the wiring board outermost layer of the fine wiring for mounting surface-mounted components such as chips reduced in size and enhanced in precision with high precision.